The present invention is directed to computer memories and, more particularly, to a method and apparatus for refreshing a dynamic random access memory (DRAM).
FIG. 1 is a schematic diagram of a typical DRAM memory cell 10 coupled to a sense amplifier 22. Memory cell 10 includes a capacitance 14 and an FET (NMOS) transistor 18. NMOS transistor 18 has a gate terminal 34 coupled to a word line 38, a first current flowing terminal 30 coupled to a terminal 26 of capacitance 14, and a second current flowing terminal 42 coupled to a bit line 46. The other terminal of capacitance 14 is coupled to a fixed voltage V.sub.x. Bit line 46 is coupled to one input terminal 50 of sense amplifier 22. Another input terminal 54 of sense amplifier 22 is coupled for receiving a reference voltage potential (V.sub.ref). Sense amplifier 22 also includes a feedback line 58 coupled to bit line 46. The data stored in memory cell 10 is determined by the charge on capacitance 14. For example, a +5 volt signal on terminal 26 may indicate a "1," and a 0 volt signal on terminal 26 may indicate a "0."
To read the data stored in memory cell 10, a signal is provided on word line 38 for turning on NMOS transistor 18 and communicating charge between capacitance 14 and bit line 46. The capacitance of bit line 46 typically is much larger than that of capacitance 14, so the voltage on bit line 46 changes only slightly. For example, if terminal 26 of capacitance 14 is at +5 volts, and if bit line 46 is initially at +2.5 volts, then, when NMOS transistor 18 turns on, the voltage on bit line 46 may rise to approximately +2.6 volts. On the other hand, if terminal 26 of capacitance 14 is at 0 volts, then, when NMOS transistor 18 turns on, the voltage on bit line 46 may fall to approximately +2.4 volts. The voltage on bit line 46 is then compared by sense amp 22 to the reference voltage applied to input terminal 54. The reference voltage may be, for example, +2.5 volts. If the voltage on bit line 46 is above the reference voltage, then a +5 volt signal is provided on feedback line 58 for raising the voltage on bit line 46 to +5 volts, thus restoring the signal on terminal 26 of capacitance 14 to +5 volts. Of course, word line 38 must be above +5 volts to charge node 30 to +5 volts. On the other hand, if the voltage on bit line 46 is less than the reference voltage, then a 0 volt signal is provided on feedback line 58 for lowering the voltage on bit line 46 to 0 volts, thus restoring the signal on terminal 26 of capacitance 14 to 0 volts. In any event, the resulting voltage on bit line 46 indicates the value of the data stored in the memory cell to the rest of the system, and the cell voltage is returned to its original condition.
Since the charge on capacitance 14 is used to indicate the value of the data stored in each memory cell 10, and since undesired leakage current slowly discharges each memory cell, it is necessary to ensure that the charge does not dissipate to a level which causes improper operation of sense amp 22. To maintain the charge at the proper level, a special cycle, termed a "refresh cycle," is performed to periodically restore the charge on capacitance 14 of all cells sharing a common word line. The refresh cycle can be simply a normal read or write cycle. That is, a signal is provided on word line 38 for turning on NMOS transistor 18, followed by sense amp 22 generating the +5 volt or 0 volt signal on bit line 46 for restoring the (previously somewhat decayed) charge on capacitance 14.
FIG. 2 is block diagram of a typical DRAM 70 which incorporates a plurality of the memory cells 10 shown in FIG. 1. DRAM 70 includes a plurality, e.g., 16 memory arrays 74A-P, a decode circuit 78, an internal signal generator 82, a multiplexer 86, and a row refresh address counter 90. Each memory array 74A-P includes a plurality of memory cells -0, each located at the intersection of word lines 38A-P and bit lines 46A-P. Only one word line and one bit line are shown for each array, and the corresponding FET transistors and capacitances are not shown for clarity. In this embodiment, there are 256 word lines and 1024 bit lines coupled to each word line per array. Thus, DRAM 70 has a total of 4,194,304 memory cells.
Internal signal generator 82 receives row address strobe (RAS) signals on a line 94, column address strobe (CAS) signals on a line 98, and external address signals on a bus 102. lnternal signal generator 82 provides the external address signals to multiplexer 86 through a bus 110. A mode control circuit 114, which may be a part of internal signal generator 82, determines whether DRAM 70 is in a normal (data reading or data writing) mode or in a refresh mode and provides address select signals to multiplexer 86 through a bus 118 and counter incrementing signals to counter 90 through a bus 122. Counter 90 provides a count value to multiplexer 86 through a bus 128. The count value functions as an address during refresh cycles, thus relieving the programmer of the duty of keeping track of which row to refresh. Multiplexer 86 thus provides the external address or the counter value to decode circuit 78 through a bus 132 in response to the address select signals received on line 118. Decode circuit 78 communicates with memory arrays 74A-P through corresponding buses 80A-P. The phantom line shown in FIG. 2 is not part of the prior art and will be discussed below.
FIG. 3A is a timing diagram showing a typical read cycle for obtaining data from DRAM 70. As usual, address multiplexing is employed to address the 4,194,304 memory cells in DRAM 70. That is, the 22-bit address is supplied in two groups of 11 bits each. Initially, the RAS signal goes low, and 11-bits of the external address (termed the "row address") are supplied on address bus 102 and latched in the DRAM. Thereafter, the CAS signal goes low, and the remaining 11 bits of the external address (termed the "column address") are supplied on address bus 102 to select one of the bit lines coupled to a selected word line. Since the column address has 11 bits, there must be 2.sup.11 bits of data to choose from. That is, at least 2048 separate bits must have been selected, sensed, and refreshed as a result of the RAS signal being activated. Thus, two word lines of 1024 bits each are selected by the row address, one in each of two of the memory arrays 74A-P. Write cycles are handled the same way.
FIG. 3B is a timing diagram showing one method for executing a refresh cycle. In this method, the CAS signal goes low before the RAS signal. Mode control circuit 114 detects the early CAS signal and generates a signal on line 118 so that multiplexer 86 provides the counter value (count N) as the row address to decode circuit 78. Decode circuit 78 decodes the counter value to activate 2 word lines, thus refreshing 2048 memory cells. Mode control circuit 114 also generates a signal on line 122 for incrementing (or decrementing) counter 90 (e.g., to count N+1). Typically, all memory cells are refreshed once every 16 milliseconds. Thus, as long as the programmer executes 2048 CAS-before-RAS cycles every 16 milliseconds, the DRAM will be fully and systematically refreshed, since the eleven-bit counter increments on each CAS-before-RAS refresh cycle. Of course, the programmer may forego the benefit of counter 90, systematically provide external addresses on address bus 102, and refresh DRAM 10 via 2048 normal read cycles every 16 milliseconds.
As technology advances, there is constant pressure to increase the number of normal read or write cycles available per unit of time to provide increased data flow. Accordingly, prior art DRAM's have been modified so that four word lines are activated per cycle (during both normal and refresh cycles) so twice as many memory cells (4096) are refreshed in every refresh cycle. Thus, only 1024 refresh cycles are needed every 16 milliseconds instead of 2048, allowing the DRAM to do useful read or write cycles during the time otherwise occupied by the extra refresh cycles. Unfortunately, almost twice as much power is consumed per cycle, and larger power supplies are needed. Furthermore, as memory speeds increase, the average power consumption becomes excessive, and the memory chips are unable to dissipate the heat without adding complex cooling systems.